This application claims the priority of Application No. 2000-354113, filed Nov. 21, 2000 in Japan, the subject matter of which is incorporated herein by reference.
The present invention relates to a driving circuit for driving an LCD (liquid crystal display) or the like.
A conventional driving circuit is designed to drive segment electrodes in, for example, a matrix type LCD. According to a conventional driving circuit, a leakage current may flow between driving voltages via an output node. Although the leakage current caused in each driving circuit is small, as the number of driving circuits is increased in association with a trend toward a larger screen of the LCD, the total power consumption is increased. The increase in power consumption associated with the trend toward the larger screen is a serious problem especially in battery-powered portable displays.
Accordingly, it is an object of the present invention to provide a driving circuit in which the problems of the prior art are solved and in which no leakage current occurs in switching of a driving voltage.
Additional objects, advantages and novel features of the present invention will be set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
To solve the above problems, according to a first aspect of the present invention, there is provided a driving circuit having a plurality of switching units for, when receiving respective corresponding driving signals, outputting driving voltages corresponding to the driving signals to a common output node, the driving circuit including a driving control unit for, when a selection signal to select the driving voltage is activated, outputting the driving signal so as to be delayed by a predetermined time period and, when the selection signal is inactivated, immediately interrupting the driving signal.
Since the driving circuit is constructed as mentioned above, the following operation is performed.
For instance, when a selection signal to select a first driving voltage is inactivated at a certain instant and a selection signal to select a second driving voltage is activated, the driving control unit immediately interrupts a driving signal corresponding to the first driving voltage, thereby interrupting the first driving voltage generated from the switching unit. On the other hand, a driving signal corresponding to the second driving voltage is generated from the driving unit so as to be delayed by a predetermined time period. Consequently, after the first driving voltage is interrupted, the second driving voltage is generated from the switching unit after the predetermined time period.
According to a second aspect of the present invention, there is provided a driving circuit similar to that of the first aspect, the driving circuit including: selecting units for selecting a first clock signal when a selection signal to select a driving voltage is inactivated and, when the selection signal is activated, selecting a second clock signal delayed in phase relative to the first clock signal; and holding units for holding the selection signal on the basis of timing of the clock signal selected by the selecting unit and supplying the held contents as a driving signal to the switching unit.
In this aspect, the following operation is performed.
For example, when a selection signal to select a first driving voltage is inactivated at a certain instant and a selection signal to select a second driving voltage is activated, the selection signal corresponding to the first driving voltage is held by the holding unit at timing of the next first clock signal and, further, the selection signal corresponding to the second driving voltage is held by the holding unit at timing of the subsequent second clock signal. Consequently, the first driving voltage is interrupted at the timing of the first clock signal and, after that, the second driving voltage is outputted at the timing of the second clock signal.
According to a third aspect of the present invention, there is provided a driving circuit similar to that of the first aspect, the driving circuit including: selecting units similar to those of the second aspect of the present invention; holding units for holding a selection signal on the basis of timing of a clock signal selected by the selecting unit; and driving control units for, when the selection signal held by the holding circuit is activated, outputting the driving signal so as to be delayed by a predetermined time period and, when the selection signal is inactivated, immediately interrupting the driving signal.
In this aspect, the following operation is performed.
For instance, when a selection signal to select a first driving voltage is inactivated at a certain instant and a selection signal to select a second driving voltage is activated, the selection signal corresponding to the first driving voltage is held by the holding unit at timing of the next first clock signal and, further, the selection signal corresponding to the second driving voltage is held by the holding unit at timing of the subsequent second clock signal. As for the selection signals held by the holding units, the driving control units control delay time and each selection signal is supplied as a driving signal to the switching unit. Consequently, the first driving voltage is interrupted at the timing of the first clock signal and, after that, the second driving voltage is outputted so as to be further delayed relative to the timing of the second clock signal.
According to a fourth aspect of the present invention, there is provided a driving circuit similar to that of the first aspect, the driving circuit including: selecting units for selecting a first clock signal when an input signal is inactivated and, when the input signal is activated, selecting a second clock signal delayed in phase relative to the first clock signal; holding units for holding the input signal on the basis of timing of the clock signal selected by the selecting unit; and a decoding unit for decoding the held contents of the holding unit to form the driving signal for selecting the driving voltage and supply the driving signal to the switching unit.
In this aspect, the following operation is performed.
For example, when an input signal is inactivated at a certain instant, the selecting unit selects the first clock signal and the holding unit holds the input signal at timing of the next first clock signal. The held input signal is decoded by the decoding unit. A driving signal as a decoding result is supplied to the switching unit, thereby interrupting the corresponding driving voltage.
On the other hand, when the input signal is activated, the selecting unit selects the second clock signal delayed in phase relative to the first clock signal and the holding unit holds the input signal at timing of the next second clock signal. The input signal held by the holding unit is decoded by the decoding unit and a driving signal as a decoding result is supplied to the switching unit, thereby outputting the corresponding driving voltage.
According to a fifth aspect of the present invention, there is provided a driving circuit similar to that of the first aspect, the driving circuit including: selecting units and holding units similar to those of the fourth aspect; a decoding unit for decoding the held contents of the holding units to form a selection signal to select the driving voltage; and a driving control unit for, when the selection signal is activated, outputting the driving signal so as to be delayed by a predetermined time period, and when the selection signal is inactivated, immediately interrupting the driving signal.
In this aspect, the following operation is performed.
For example, when an input signal is inactivated at a certain instant, the selecting unit selects the first clock signal and the holding unit holds the input signal at timing of the next first clock signal. On the other hand, when the input signal is activated, the selecting unit selects a second clock signal delayed in phase relative to the first clock signal and the holding unit holds the input signal at timing of the next second clock signal.
The input signal held by the holding unit is decoded by the decoding unit, thereby forming a selection signal to select a driving voltage. The selection signal is supplied to the driving control unit. In the inactivation, the driving signal to immediately interrupt the driving voltage is supplied to the switching unit and, in the activation, the driving signal to output the driving voltage so as to be delayed by a predetermined time period is supplied to the switching unit.
Preferably, in the first, third, or fifth aspect of the present invention, the driving control unit is constructed by logic gates each having an output unit obtained by serially connecting complementary MOSs having different mutual conductance from each other.
According to a sixth aspect of the present invention, there is provided a driving circuit for outputting any one of a plurality of driving voltages to a common output node, the driving circuit including: a driving signal output circuit for outputting a plurality of driving signals corresponding to the plurality of driving voltages on the basis of a plurality of selection signals; and a plurality of switching units, which are controlled by the plurality of driving signals, respectively, for outputting the driving signal corresponding to any one of the plurality of driving voltages to the output node, wherein the driving signal output circuit is constructed so as to generate the plurality of driving signals to allow a transition from an ON state to an OFF state of the switching unit to be faster than that from the OFF state to the ON state thereof.
Preferably, in the sixth aspect, the driving signal output circuit has a first conductivity type first MOS coupled between an output terminal thereof and a power supply potential and a second conductivity type second MOS coupled between the output terminal and a ground potential, when the switching unit is a first conductivity type MOS, the ratio of gate length to gate width of the second MOS is larger than that of the first MOS, and when the switching unit is a second conductivity type MOS, the ratio of gate length to gate width of the first MOS is larger than that of the second MOS.
Preferably, in the sixth aspect, the driving signal output circuit has a first conductivity type first MOS coupled between an output terminal thereof and a power supply potential and a second conductivity type second MOS coupled between the output terminal and a ground potential, when the switching unit is a first conductivity type MOS, the ratio of gate width to gate length of the second MOS is smaller than that of the first MOS, and when the switching unit is a second conductivity type MOS, the ratio of gate width to gate length of the first MOS is smaller than that of the second MOS.
Preferably, in the sixth aspect, the driving signal output circuit has a first conductivity type first MOS coupled between an output terminal thereof and a power supply potential and a second conductivity type second MOS coupled between the output terminal and a ground potential, when the switching unit is a first conductivity type MOS, the ON resistance of the second MOS is larger than that of the first MOS, and when the switching unit is a second conductivity type MOS, the ON resistance of the first MOS is larger than that of the second MOS.
Preferably, in this aspect, the driving signal is generated so as to control the switching unit on the basis of one of a first clock signal and a second clock signal delayed in phase relative to the first clock signal, when the driving signal allows the switching unit to change from the OFF state to the ON state, the driving signal is outputted on the basis of the second clock signal, and when the driving signal allows the switching unit to change from the ON state to the OFF state, the driving signal is outputted on the basis of the first clock signal.
Preferably, the driving circuit according to this aspect includes: clock signal selecting units for selecting either one of the first and second clock signals; selection signal holding units for holding the selection signal on the basis of the first or second clock signal selected by the clock signal selecting unit; and a decoding unit for decoding the held contents of the selection signal holding unit to form the driving signal corresponding to the driving voltage.
According to this aspect, the following operation is performed.
The driving signal to allow the transition from the ON state to the OFF state to be faster than that from the OFF state to the ON state is outputted from the driving signal output circuit to the switching unit. Consequently, a fear of simultaneously turning on the plurality of switching units is eliminated.
According to a seventh aspect of the present invention, there is provided a driving circuit for outputting one of first and second driving voltages to a common output node, the driving circuit including: a first driving signal output circuit for outputting a first driving signal corresponding to the first driving voltage on the basis of a first selection signal; a second driving signal output circuit for outputting a second driving signal corresponding to the second driving voltage on the basis of a second selection signal; a first switching unit, which is controlled by the first driving signal, for outputting the first driving voltage to the output node; and a second switching unit, which is controlled by the second driving signal, for outputting the second driving voltage to the output node, wherein the first and second driving signal output circuits output the first and second driving signals for allowing a transition from an ON state to an OFF state of the second switching unit to be faster than that from the OFF state to the ON state of the first switching unit, respectively.
Preferably, in the seventh aspect, one of the first and second driving signal output circuits has a first conductivity type first MOS coupled between an output terminal thereof and a power supply potential and a second conductivity type second MOS coupled between the output terminal and a ground potential, when one of the first and second switching units is a first conductivity type MOS, the ratio of gate length to gate width of the second MOS is larger than that of the first MOS, and when one of the first and second switching units is a second conductivity type MOS, the ratio of gate length to gate width of the first MOS is larger than that of the second MOS.
Preferably, in the seventh aspect, one of the first and second driving signal output circuits has a first conductivity type first MOS coupled between an output terminal thereof and a power supply potential and a second conductivity type second: MOS coupled between the output terminal and a ground potential, when one of the first and second switching units is a first conductivity type MOS, the ratio of gate width to gate length of the second MOS is smaller than that of the first MOS, and when one of the first and second switching units is a second conductivity type MOS, the ratio of gate width to gate length of the first MOS is smaller than that of the second MOS.
Preferably, in the seventh aspect, one of the first and second driving signal output circuits has a first conductivity type first MOS coupled between an output terminal thereof and a power supply potential and a second conductivity type second MOS coupled between the output terminal and a ground potential, when one of the first and second switching units is a first conductivity type MOS, the ON resistance of the second MOS is larger than that of the first MOS, and when one of the first and second switching units is a second conductivity type MOS, the ON resistance of the first MOS is larger than that of the second MOS.
Preferably, in this aspect, the first and second driving signals are outputted so as to control the first and second switching units on the basis of one of a first clock signal and a second clock signal delayed in phase relative to the first clock signal, when the first switching unit changes from an OFF state to an ON state by the first driving signal, the first driving signal is outputted on the basis of the second clock signal, and when the second switching unit changes from the ON state to the OFF state by the second driving signal, the second driving signal is outputted on the basis of the first clock signal.
Preferably, the driving circuit according to this aspect includes: clock signal selecting units for selecting either one of the first and second signals; first and second selection signal holding units for holding the first and second selection signals on the basis of one of the first and second clock signals selected by the clock signal selecting unit, respectively; and first and second decoding units for decoding the held contents of the first and second selection signal holding circuit to form the first and second driving signals corresponding to the first and second driving voltages, respectively.
According to this aspect, the following operation is performed.
The first driving signal to switch the switching unit from the OFF state to the ON state is generated from the first driving signal output circuit to the first switching unit. The second driving signal to switch the switching unit from the ON state to the OFF state is generated from the second driving signal output circuit to the second switching unit. On the basis of the first and second driving signals, the second switching unit is first turned off and, after that, the first switching unit is turned on. Consequently, there is no fear that the first and second switching units are simultaneously turned on.